Technology advances and integration of a broad spectrum of IP continues to push the limits of power in all semiconductor applications. The diversity of defect types is compounding, driven by the pace of semiconductor processing complexity and IP integration. The plethora of defect types poses severe challenges to the mandate to enhance product quality and reliability with each new product release to the marketplace. Accelerating and detecting these defects at the plant of manufacture is paramount to achieving the demands of the marketplace.
Traditional semiconductor device manufacturing techniques, e.g., “burn-in” techniques, of applying a stress uses “combinational” stimuli (e.g., high voltage and high temperature applied simultaneously) and sustained for the stress duration. Defects accelerated primarily by voltage (i.e. electromigration) or primarily by thermal cycle (i.e. metal fatigue) are sub optimally stressed. An example of electromigration calculations highlights the need for maximum achievable voltage. Lower voltages require unachievable durations. Higher voltage accelerates this defect type most effectively, so reducing temperature to increase voltage enables users to accelerate defects that are “escapes” to stress at lower temperature.
Currently there exist no techniques that can be used to perform a specific optimization of stimulus, observe-ability, and/or acceleration of defects in general or specific defects. Nor are there specific techniques for integrated stimulus, observe-ability, and/or acceleration applied techniques towards an optimized defect specific process.
Accelerating this growing kaleidoscope of latent defects, against a backdrop of increasing power, circuit, and process complexity, demands a kaleidoscope of acceleration solutions.